1. Field of the Invention
The present invention relates to communication-control equipment that has a DMA (direct memory access) function.
2. Prior Art
FIG. 1 is a block diagram showing a configuration of a conventional data processing circuit 100. In FIG. 1, numeral 1 designates an ALU (Arithmetic and Logic Unit) that has a common computing function but does not have a function for handling the bus state (empty or busy), and numeral 2 designates a read/write memory. Numeral 3 designates a DMA controller which responds to a DMA request from outside and produces control signals for controlling transfer of input data to memory 2 or output data therefrom. Numeral 4 designates a DMA control register which includes a request bit RQ and an acknowledge bit AK. Request bit RQ is set by a DMA request, while acknowledge bit AK indicates that DMA is under operation. ALU 1, memory 2, and DMA controller 3 are interconnected through data bus DB and address bus AB. Address bus AB specifies an address of memory 2 by using address data thereon. Data bus DB transfers data between memory 2 and ALU 1, or between memory 2 and an external storage via DMA controller 3. Each of address bus AB and data bus DB is provided with switches SW along the way, and ALU 1 can communicate with memory 2 when switches SW are in the "on" state.
The operation of data processing circuit 100 is as follows:
In the normal operation mode, request bit RQ and acknowledge bit AK in DMA control register 4 are both "0". Switches SW are in the "on" state, because acknowledge bit AK is "0", and ALU 1 is connected to memory 2 through address bus AB and data bus DB. As a result, ALU 1 can communicate with memory 2 to read or write data.
When DMA request signal HLDRQ is provided to DMA controller 3, request bit RQ in DMA control register 4 is set by DMA controller 3. When ALU 1 detects request bit RQ being set and is not using memory 2 at that time, ALU 1 sets acknowledge bit AK, and turns off switches SW to disconnect ALU 1 from memory 2. DMA controller 3 also detects request bit RQ being set, and outputs DMA acknowledge signal HLDAK to indicate that the DMA is granted. After that, the DMA operation is carried out as follows:
When data from outside are written to memory 2, DMA controller 3 reads data in an external memory not shown and places the data on data bus DB. At the same time, DMA controller 3 supplies a write address to memory 2 via address bus AB. The data on data bus DB is written to the designated address in memory 2. On the other hand, when data in memory 2 are written to an external memory, DMA controller 3 supplies read address to memory 2 via address bus AB, reads the data of the designated address in memory 2, and transfers the read data through data bus DB. This data is transferred under the control of DMA controller 3 and is written into the external memory.
When the DMA operation above is completed, DMA controller 3 resets acknowledge bit AK in DMA control register 4. As a result, switches SW are turned on again, connecting ALU 1 and memory 2. Thus, ALU 1 can communicate with memory 2 to transfer data.
The conventional data processing circuit 100, however, has a following disadvantage: ALU 1 cannot access memory 2 during the DMA operation because ALU 1 is disconnected from memory 2. As a result, ALU 1 cannot execute the process until the DMA operation is completed. This hinders an application of the conventional data processing circuit to a circuit such as communication-control equipment that necessitates a real time process.